FPGA implementation of min-sum algorithm for LDPC decoder
P.V. Sreemohan, Nelsa Sebastian · 2017 International Conference on Trends in Electronics and Informatics (ICEI) · 2017
Low-density parity-check codes (LDPC) are among the most powerful error correcting tools today available. In this paper, it has aimed a Field Programmable Gate Array (FPGA) implementation of LDPC decoder with less complexity. The proposed decoding structure reduces complexity of the check node unit (CNU) and the variable node unit (VNU) based on min-sum (MS) algorithm, thereby achieving less slice resources. A multiplexed storage structure is used for the storage of node messages which results in less slice resources. Hardware resources act as a crucial factor in many applications like deep space communications and its efficient utilization is an area which is highly explored. Both high performance and low complexity are expected from LDPC decoders used in space data systems. This low-complexity implementation is an efficient method to achieve the requirements put forward by many wired and wireless communication systems.