Bit-vector pattern matching systems on the base of high bandwidth FPGA memory
Alexander V. Alyushin, Sergey A. Alyushin, Vasilii G. Arkhangelsky · 2018
2D distributed structure of the FPGA internal memory elements with extremely high bandwidth (up to 1270 Tbps in total for Xilinx Virtex family) makes them very promising for rapid big-data pattern matching systems implementations on the base of look-up engine. Bit-vector technique effectively spreads big look-up data table among memory blocks of limited size. Developed by the authors multi-cluster approach permits to realize rapid look-up engine with parallel access to almost all FPGA memory elements far located from each other on the surface of the chip. Low system time delay memory access is very important for such time delay sensitive high bandwidth applications as bio-inspired artificial neural nets, track pattern reconstruction in a particle-physics experiment, network packet classification, computer and network security. For bigger look-up tables time delay analysis of the external memory blocks with parallel and serial links (up to 150 Gbps) is given. The aspects of a multilevel information protection, IA (Information Assurance), R2 (Reusable and Reliable) design flow for FPGA pattern matching system with high bandwidth internal and external memory are discussed.