Design and Operational Synthesis of 64-bit Adder and Subtracter Unit using Delay Efficient Parallel Prefix Technique
Akash Tiwari · International Journal for Research in Applied Science and Engineering Technology · 2018
Digital design of the various arithmetic circuits often finds the applications in various devices and processes.Various circuits like adder, Subtractors, and multipliers are being used in various digital circuits.BCD arithmetic circuits are also widely used in various communication devices and often find the advantages in a lot of storage media and compatible for various industrial devices.In this work, we have proposed the design of the 64-bit BCD Adder and Subtractor using reversible logic circuits and high speed modified design has been presented.Here, we have used Peres gate for the design using Kogge-stone adder which decreases the delay in addition processes.For the adder, we have used the converter modules.Here, we have simple binary adder module, in combination with the error correction circuit and low power binary to BCD modules.We have used parallel prefix architecture for the adder/Subtractor design and delay efficient algorithm for the Subtractor.The suggested system design has been design using Model sim 10.3d, synthesized using Xilinx 14.1 for the low power KINTEX-7 KC705 FPGA Evaluation Platform as target module and for power consumption X power analyser has been utilized.The Kintex family uses 28nm (nanometer) design technology which utilizes only half of the lower power than the other compared technologies.