FPGA implementation of encoder and decoder for Golay code
Allan José, S. Sujithamol · 2017 International Conference on Trends in Electronics and Informatics (ICEI) · 2017
An efficient high-speed encoding scheme of binary Golay code (23, 12, 7) along with its design and implementation in Spartan-6 FPGA is presented in this paper. For the proposed encoder, a low latency is achieved by excluding linear feedback shift register (LFSR) in the design. Also, a low-complexity binary Golay decoder based on syndrome decomposition algorithm and add-compare computation with parallel architecture is proposed which results in high speed operation. The proposed architecture works at an improved speed when compared to the contemporary works published in this area. A clock frequency of 344.827 MHz is observed for the proposed encoder architecture while the decoder has a speed of 318.471 MHz. For the proposed hardware modules both high throughput and low latency is achieved.