A novel congestion-aware and adaptive routing algorithm in mesh-based Networks-on-Chip with segmentation
Reza Akbar, Farshad Ramezan Pour Safaei · 2017
The networks on chip (NoC) have been presented as a viable and scalable solution for connecting the processor cores in a multi-core chip. In recent years, with increasing the number of cores in NoCs, the congestion has been raised as a key and bottleneck for achieving proper efficiency. In this paper, we first segment the NoC into a number of subnets and then provide a congestion-aware algorithm with three main phases based on this segmentation. The segmentation and usage of the proposed algorithm can improve the system performance compared to the previous work. This algorithm is compared with the DyXY, DyAD and CATRA algorithms and the superior results are obtained. Under SPLASH-2 traffic patterns, the average packet latencies have been improved by 13.3%, 10.6%, and 17.8%, respectively compared to DyXY, DyAD and CATRA algorithms. Moreover, in the same traffics, the proposed algorithm consumes less power compared to these algorithms. In fact, it can be whispered that the proposed scheme has not worsened in power consumption. This improvement has also been observed under synthetic traffics. In addition to present a novel algorithm, a new parameter, the variance of crossbar activity, is suggested as a parameter to assess the performance of congestion-aware routing algorithms. Compared to DyAD and CATRA, it is showed that this parameter has been enhanced in the proposed algorithm by 32.4% and 50.2%, respectively.