Research and development of the PLL loop for the implementation of ADC based on nanoscale technologies
Rafael Magerramov · 2018
The ADCs characteristics that make up the MC don't always correspond to the specified requirements for accuracy and noise level. The thesis paper describes a new type of ADC with phase-locked loop (ADC with PLL). Currently, the development of a number of electronic devices is conducted jointly with the use of various microcontrollers (MK), which includes analog-digital converters (ADCs). A new type of ADC allows improve these characteristics, having a relatively simple circuit design implementation. Using the PLL loop, the input level voltage (analog signal) is converted into a digital frequency signal of a variable pulse ratio. The converted signal (analog voltage) is applied to one of the low-pass filter (LPF) inputs included in the PLL, thereby removing the circuit from equilibrium, changing the pulse ratio of the output signal.