An efficient method for reconfiguring power‐efficient VLSI array with maximum satisfiability
Junyan Qian, Cong Chen, Lingzhong Zhao, Yunchuan Guo · IEEJ Transactions on Electrical and Electronic Engineering · 2018
Techniques to determine subarrays when processing elements (PEs) of very large scale integration (VLSI) arrays become faulty have been investigated extensively. In this paper, we propose a maximum satisfiability (MaxSAT)‐based method for the reconfiguration of a two‐dimensional degradable VLSI array with faulty PEs. A MaxSAT model is developed such that the target array can be constructed utilizing the efficient MaxSAT solver. Using the proposed method, we are able to find a maximum logical array with the least number of long interconnects and minimizing the number of the long interconnects that will lead to less rerouting costs. Experimental results show that the proposed method is able to reduce most redundant interconnects for the host array compared to earlier works. © 2018 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.