Study of spectral purity dependence on sine-ROM size in a digitally controlled frequency synthesizer
M. C. Parameshwara, H. C. Srinivasaiah · 2017
In this paper the spectral purity of the sine-ROM (SROM) based Digitally (or Numerically)-controlled-Frequency-Synthesizer (DCFS or NCFS) architecture is analyzed in terms of its spurious-free-dynamic-range (SFDR) metric as a function of its SROM address bus width, M (bits), its data bus width, Z (bits), "binary-frequency-control-word" (BFCW) size, and "Reference clock frequency", fclk. The M is varied from 10 to 13 bits; the Z is varied from 2 to 11 bits, which is the digitized input to the "digital-to-analog-converter" (DAC) applied with its word size W (= Z + 1) bits. Accordingly the W is varied from 3 to 12 bits, whose "most-significant-bit" (MSB) is used to offset the DAC's output to 50% of its supply voltage. The parameter BFCW has the following discrete values: 32'h00100000, 32'h01000000, 32'h01010001, and 32'h10000000 corresponding to synthesized frequency ft): ~0.122 MHz, ~1.95 MHz, ~ 1.961 MHz, and ~31.25 MHz, respectively. The highest SFDR observed in the above parameter space is 75.69 dBc corresponding to BFCW = 32'h00100000 yielding fout= 0.122 MHz for M =13 bits, and W = 12 bits. The lowest SFDR observed in this space is ~22.35 dBc corresponding to BFCW = 32'h10000000 resulting in fout= 31.25 MHz, for M =11 bits and W = 4 bits. Further, the SFDR is also found to be a weak function of fclk, between 0.5 GHz to 3.3 GHz when observed for all the above 4 BFCWs. All these simulations are run in a technology independent Verilog-"analog-mixed-signal" (AMS) environment of Cadence's EDA tool to characterize this SROM based DCFS architecture in the above parameter space.