Implementation of single precision conventional and fused floating point add-sub unit using Verilog
Aditi Sharma, Sukanya Sukanya, Abhay Sharma · 2017
Floating-point arithmetic is enhancive for the realization of a vast application of Digital Signal Processing (DSP) such as Fast Fourier Transform, Discrete Cosine Transform. In this paper, architecture of floating point adder and floating point Subtractor were compared with their fused counterpart known as Fused Addition-Subtract Unit. Since, most of the DSP algorithms require FFT and DCT in their structures hence analysis and implementation were done specifically for complex addition and subtraction involved in FFT computation. Butterfly unit consisting of arithmetic operations like additions, subtractions and multiplications of complex valued data were first implemented using conventional single precision floating point adder and Subtractor. Thereafter, single compressed structure for floating point addition-subtraction was implemented using Verilog HDL. After simulation run on Xilinx ISE tool, it was observed that fused Add-Sub FPU provides better latency results compared to conventional FPU.