An Area-efficient Half-row Pipelined Layered LDPC Decoder Architecture
Sabooh Ajaz, Tram Thi Bao Nguyen, Hanho Lee · JSTS Journal of Semiconductor Technology and Science · 2017
This paper presents an area-efficient half-row pipelined layered low-density parity check (LDPC) decoder architecture for IEEE 802.11ad applications. The proposed decoder achieves a good tradeoff between throughput and area because of its ability to overcome the low-throughput bottleneck in conventional half-row decoders and the high-complexity bottleneck in fully parallel decoders. Synthesis results using TSMC 40 nm CMOS technology shows much better throughput at 10.84 Gbps and superior area efficiency, compared to previously reported LDPC decoders.