Design of high-throughput SHA-256 hash function based on FPGA
Shamsiah binti Suhaili, Takahiro Watanabe · 2017
Nowadays, security has become an important topic of interest to researchers. Different types of cryptography algorithms have been developed in order to improve the performance of these information-protecting procedures. A hash function is a cryptography algorithm without a key such as MD5, RIPEMD160, and SHA-1. In this paper, a new SHA family is developed and designed in order to fulfil the cryptographic algorithm performance requirement. Thus, SHA-256 design and SHA-256 unfolding design based on reconfigurable hardware have been successfully completed using Verilog code. These designs were simulated and verified using ModelSim. The results showed that the proposed SHA-256 unfolding design gave better performance on Arria II GX in terms of throughput. The high throughput of SHA-256 unfolding design was obtained at a data transfer speed of 2429.52 Mbps.