A 5.5 MIPS call handling processor for switching systems
Morita, Hayashi, Saita, Ohno, Yoshida, Fukuda, Ikeda · 1988
A 32-bit Processor for ESS (Electronic Switching Systems) with mixed (RISC & CISC) instruction set is described. The performance is achieved by a 4-stage Pipeline and the local storage for RISC like instructions and by WCS (Writable Control Storage) for CISC like instructions at 16MHz. Using 1.2micron double metal CMOS technology. the chip contains 160K transistors on a 13.2x13.7 mm die.