A fuzzy logic inference processor
John W. Fattaruso, Shivaling S. Mahant-Shetti, Jeffrey B. Barton · IEEE Journal of Solid-State Circuits · 1994
A mixed analog-digital fuzzy logic inference engine chip fabricated in an 0.8 /spl mu/m CMOS process is described. Interface to the processor behaves like a static RAM, and computation of the fuzzy logic inference is performed between memory locations in parallel by an array of analog charge-domain circuits. Eight inputs and four outputs are provided, and up to 32 rules may be programmed into the chip. The results of the inference over all rules, including a center-of-mass defuzzification, may be computed in 2 /spl mu/s.>