A fully-pipelined single-precision floating point unit in the synergistic processor element of a CELL processor
Hwa-Joon Oh, Silvia Melitta Mueller, Christian Jacobi, Khoa Dac Tran, S. Cottier, B.W. Michael, Hiroaki Nishikawa, Y. Totsuka, T. Namatame, Naoka Yano, T. Machida, S.H. Dhong · 2005
The floating point unit in the synergistic processor element of a CELL processor is a fully-pipelined 4-way SIMD unit designed to accelerate media and data streaming. It supports 32-bit single-precision floating point and 16-bit integer operands with two different latencies, optimizing the performance of critical single-precision multiply-add operations. It employs fine-grained clock gating for power saving. Architecture, logic, circuits and integration are co-designed to meet the performance, power, and area goals.