Evaluation of CGRA architecture for real-time processing of biological signals on wearable devices
João D. Lopes, Diogo Sousa, João Canas Ferreira · 2017
This paper describes the design and implementation of a coarse-grained reconfigurable array (CGRA) for low-power biological signal processing. It uses an use-case-driven approach which explores the application domain and gathers common requirements. The selected CGRA core architecture is implemented using a standard-cell flow (in a generic 90 nm CMOS process), so that the CGRA can be totally or partially turned off by power gating. The selected CGRA design is evaluated for two use-cases using layout information and accurate node activity information. The resulting accelerator is capable of performing various signal processing tasks very efficiently, achieving an average power consumption of 19.9pJ/cycle (or 1.99 mW at 100 MHz). Static power consumption for less intensive tasks can be reduced by using only some sections of the CGRA while powering-off others.