Fault Sensitive Neutralization of Hardware Trojans Using Multi-level Triple Modular Redundancy Scheme
Nagendra Babu Gunti, Karthikeyan Lingasubramanian · 2017
Hardware Trojans are malicious alterations in Integrated Circuits (ICs) that leaks confidential information or disables the entire IC. The detection of these Trojans is performed through logic or side channel based testing. Under sub-nm technologies this kind of detection will face more problems due to process variations. Therefore there is a need to address these vulnerabilities without relying on their detection. In this work we propose to neutralize the effect of Trojans by leveraging fault tolerant design methodologies like Triple Modular Redundancy (TMR) for security. Under this context a Fault can also be caused by a man made Trojan as compared to natural sources. To comprehensively address all these faults single TMR implementation is not helpful. In this work, a more efficient TMR approach to neutralize Trojans in the presence of natural faults is accomplished through multiple levels of TMR implemented after logic partitioning. We have diagnosed this approach for ISCAS'85 benchmark circuits of nodes within 900 and observed an improved Trojan Neutralization Rate (TNR). Our experiments show that the interplay of Trojan and natural faults actually reduces TNR. We have also shown that the Implementation of 3 levels of TMR considerably improves TNR.