Evaluation of FPGA design tools for safety systems with on-chip redundancy referring to the standard IEC 61508
Emil Gracić, Ali I. Hayek, Josef Börcsök · 2017
Internet of Things and Industry 4.0 lead to great possibilities of technical innovations but also to great risks and hazards. Not only the data has to be secured, but also the processing systems have to be more reliable and safe. From this perspective, implementation of safety related systems based on separated chip dies should belong to the past. ASIC developers have already designed diverse redundant system architecture on a single chip die. In last four years major FPGA manufacturers, Xilinx and Intel Altera, have been trying to establish a concept for implementing of redundant systems on a common FPGA. This study evaluates such concepts and conducts a comparative analysis with the requirements of international safety standard IEC 61508. Respectively, it argues with empirical results and discusses why the statements about reaching a SIL3 on FPGA platform are recently controversial. To resolve this kind of limitation, this research work proposes new conceptual modifications of current FPGA structure.