FPGA accelerates deep residual learning for image recognition
Xuelei Li, Liangkui Ding, Li Wang, Fang Cao · 2017 IEEE 2nd Information Technology, Networking, Electronic and Automation Control Conference (ITNEC) · 2017
Deep learning is greatly promoting the fast development of artificial intelligence. In the image classification area, the recognition rate and inference performance become the main challenges in the real application. Recently, residual network (ResNet) has shown a competitive accuracy and nice convergence behaviors in deep neural networks. In this paper, we are devoted to accelerate this promising framework in the inference application on FPGA (Field Programmable Gate Array) using OpenCL programming language. Firstly, a supplemented deep learning accelerator is constructed to realize the residual function in ResNet. Secondly, our construction reschedules three on-chip buffers in order to store the feature data and to stream it to processor elements alternately. In addition, we also implement data parallel and pipeline execution such that the filter parameters can be synchronously processed with the image data on FPGA. Moreover, we exploit a convertor to transform any ResNet in CAFFE framework into FPGA platform. It can generate the FPGA head files using its original prototxt files through the dictionary function of Python. The experiment result analysis shows that our acceleration has a competitive performance while maintaining the high accuracy rate. Finally, we provide a solution to accelerate any construction of ResNet using OpenCL programming language on FPGA.