Design of high performance reliable network on chip router
Sameeksha. A. Ujjainkar, Bharati B. Sayankar · 2017
Uninterrupted Advancing of CMOS process technology allows to integrate multiple miniature devices over a single chipset for efficient and quality communication and facilitate the development of multiprocessors system-on-chip connected by the network-on-chip (NOC). However, this integration brings about some trust issues and performance challenges for this device. In this paper, we put forward reliable on chip router with high performance and router with lower cost design which uses generic 2-stage router, by using VHDL coding. The router we put forward varies significantly from the already available reliable routers, and hence our device can sustain its performance under heavy network loads as we make use of optimization technique and routing algorithm. Our device also has an added benefit of lower hardware consumption than that of the one which is already in use. We plan to implement VCT technique for network on chip architecture. We also propose to design and implement VCT router by using Xilinx ISE 13.1.