VLSI design of 128 point finite field FFT multiplier
Anuja Aravind, Senthil Murugan V · 2017
The purpose of this paper is to design a 128 point finite field FFT multiplier for data privacy with computation reduction. The elements in the finite field make multiplication to be simple shift and xor operation. Any given input is converted into finite field domain and it is undergoing FFT multiplication. Finite field FFT is applicable in cryptography with different key size. Arithmetic operation in the encrypted message and checksum secure the data privacy. Complexity of error checking in complex domain is manipulated by finite field system design. The structure which determine the primitive root is an integral part in accurate and accelerated output. The proposed design code can be implemented in Matlab simulator and it is verified by using Verilog simulator.