A multiplier less VLSI architecture of modified lifting based 1D/2D DWT using speculative adder
Anirban Chakraborty, Debolina Chakraborty, Ayan Banerjee · 2017
This paper presents a fast, cost effective, area efficient, multiplier less and pipelined VLSI architecture of 1D and 2D Discrete Wavelet Transform (DWT). We have proposed 1D DWT architecture, based on a novel existing modified lifting based algorithm. Our proposition outperforms other available lifting algorithm based architectures as in the literature in terms of hardware requirement and operating frequency. This is achieved by maintaining comparable latency and throughput. Area of our design is reduced, introducing a pipelined shift and add unit instead of multiplier. Speed is also enhanced by diminishing critical path delay to less than one adder delay (a) using a recently invented exceptionally faster, non-conventional speculative adder. Our design is capable of operating at such a high frequency where other existing designs cannot be able to operate satisfactorily. We have extended our proposition for the design of 2D DWT architecture elegantly using our 1D DWT pipelined architecture. In 2D DWT, we have used an innovative block based Z type memory scanning method at our own way for reducing total processing time. A two channel parallelism is incorporated in a cost effective way into 2D DWT architecture to produce less number of processing cycles along with double throughput in comparison with other existing designs.