BSD adder for floating point arithmetic: A review
Rohita Watpade, Prasanna Palsodkar · 2017
Now a days, modification in floating point architectures is very demanding area for researchers so there is always a challenge to design an efficient Floating Point Architecture. Out of any other operation, Floating Point Addition has been very popularly used. This paper presents the highly efficient BSD adder for effective way to present fast addition. Using this BSD adder in the computation algorithm of FFT Butterfly Architecture, can enhance the efficiency and at the same time can reduce the complexity, area, power consumption and delay. Starting from the design of 2 bit BSD adder we went up to design of 58 bit BSD adder as presented in this paper. BSD adder is implemented in Verilog HDL and targeted to three different families FPGA: Spartan6, Virtex5 and Virtex6 in Xilinx 13.2 ISE software. The main aim is to speed up the circuit by reducing delay have been achieved.