Thorough analysis of PCIe Gen3 communication
Hiroki Nakamura, H. Takayama, Yoshiki Yamaguchi, Taisuke Boku · 2017
This article tries a thorough analysis from the physical layer to the transaction layer on PCIe Gen3 communication by using FPGAs. First, this article shows the performance variation of PCIe Gen3 throughput on several system configurations with FPGAs. Through the experiment using four kinds of chipsets, eight types of motherboards, and three kinds of FPGAs, the performance degradation was about eight percents and fifteen percents in the identical system configurations and different system configurations, respectively. Second, this paper tried to unveil the reason why the performance decreases and to identify where the bottleneck is. The eye scan can investigate the signal quality of a link. Although the comparison of eys-scan results could explain the reason why PCIe performance degraded, it did not become the primary reason for PCIe performance variance. Then, by the use of a protocol analyzer, this article tried to find out the problem in PCIe packets. It found an unintended partitioned transaction, and this seemed to be a significant factor that reduces PCIe throughput. Lastly, this article confirms the reason for performance degradation and the performance degradation was organized quantitatively.