A low-area based costas loop implementation for BPSK signals
Sushma, Venkataratnam, Siva Sankar Yellampalli · 2017 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT) · 2017
Modulation and Demodulation are the most critical blocks in a communication system. Demodulators used in coherent communication receivers not only get back the message signal, but also perform phase error detection and correction. Phase error detection and correction involves tuning or adjusting the phase of the reference signal to that of the carrier signal received. This is an iterative process. One of the popular techniques employed for phase error detection and correction is the Costas Loop. There has been research about Numerically Controlled Oscillators (NCO) based on CORDIC algorithm being used in a Costas Loop [1]. The other simple yet memory expensive alternative to the CORDIC algorithm is to use a LookUp Table (LUT) based technique. This paper tries to model a Costas Loop based on each of the methods separately and then compare the results. There has been notable work involving the use of symmetric FIR filters in a Costas Loop [2] which saves on memory. However there has been no attempt to compare the results of folded filter (uses one half of the filter coefficients only) architecture versus that obtained from unfolded filter (uses the entire coefficient sequence) architecture implementations. This paper compares the results obtained from folded filter implementation versus that obtained from unfolded filter implementation. The system was simulated using MATLAB and Simulink. The Verilog implementation was programmed on Spartan 3e FPGA board.