Implementation of 5–32 address decoders for SRAM memory in 180nm technology
B N Bagamma, K. S. Vasundara Patel, Prasad Ravi · 2017 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT) · 2017
SRAM memories are very important building blocks of most of the digital applications like microprocessors and different levels of cache memories [8], of which Address decoders are the significant components. They play a crucial part in decoding the addresses. These decoders will decide the capacity of memory cells as well as efficiency of read operations. Hence the performance of SRAM memory also depend upon these address decoders. This paper studies the already existing type of decoders for SRAM memory. Traditional address decoders consume almost 50% of the total power and time of memory chip. An efficient and modified address decoding topology is implemented which counts the least number of transistors in order to reduce the range of SRAM using only one 2–4 decoder, 3–8 decoder and row decoders in CMOS 180nm technology using cadence virtuoso tool, and is compared with different types of decoders.