Design and Implementation of an EG-Pool Based FPGA Formatter with Temperature Compensation
Yang-Kai Huang, Kuan-Te Li, Chih-Lung Hsiao, Chia-An Lee, Jiun-Lang Huang, Terry Kuo · 2017
With modern FPGAs' reconfiguration flexibility and abundant resources, FPGA-based test equipment has become a promising solution for low to mid-end test and measurement applications. However, FPGA structure and specifications limit the choice of tester architecture and achievable performance. In this paper, we design and implement an FPGA-based multi-channel data/timing formatter, a key component in automatic test equipment. The proposed formatter (1) adopts the EG (edge generator) pool concept to improve hardware utilization, (2) employs accuracy-driven EG scheduling to improve edge placement accuracy, (3) embeds a delay monitor for temperature compensation, and (4) allows inter-channel skew adjustment. A prototype five-channel formatter is implemented on Xilinx Spartan-6 FPGA. The per channel symbol rate is 100 Msps and the edge placement resolution is 200 ps.