Testing of Interconnect Defects in Memory Based Reconfigurable Logic Device (MRLD)
Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Masayuki Sato, Mitsunori Katsu, Shoichi Sekiguchi · 2017
Recently, reconfigurable devices are gaining increased attention for the development of IoT, Automotive and AI system. A new type of fine-grained reconfigurable device named MRLD (Memory Based Reconfigurable Logic Device) has been proposed which is constructed by general SRAMs without any programmable interconnect resources. It should be a promising alternative to FPGA with the benefits of low production cost, low power and small delay. In this paper, we overview the architecture and the operation principle of MRLD. We also propose a test strategy and algorithms of pattern generation for the interconnect defects referred to stuck-at and bridge faults under MRLD. Experimental results confirmed the effectiveness of the proposed test method.