An IP core integration tool-flow for prototyping software-defined radios using static dataflow with access patterns
Lekhobola Tsoeunyane, Simon Lucas Winberg, Michael Raymond Inggs · 2017
The current design practices for prototyping Software Defined Radio (SDR) applications using reconfigurable FPGA platforms often rely on the reuse of Intellectual Property (IP) processing cores. This design practice usually involves stitching together these IP blocks to formulate a working system. High-level Synthesis (HLS) tools that support IP core integration often do not fully allow for capturing critical application timing constraints nor provide mechanisms to automatically adjust integrating logic to maintain these constraints. Consequently, reusing IP cores tends to involve many manual and time-consuming design tasks, often at a low level of abstraction. Moreover, these tasks may need to be repeated during the development process. To address these problems, we present a new open tool-flow, built upon the Delite compiler infrastructure. Central to our tool-flow is an automated mechanism for interconnecting a selection of IP cores that maintain particular application timing constraints. A crucial part of our approach and the focus of this paper is the way this tool-flow uses a static dataflow with access patterns (SDF-AP) model to efficiently capture precise timing for aspects of the processing chain. We demonstrate the capability of our tool-flow by generating six typical SDR applications in VHDL. We show how slight modifications to a design, which would have previously needed many manual adjustments, can be carried out quickly using this tool-flow. To evaluate our tool-flow, we compare performance and area results of our tool-generated SDR designs with equivalent hand-coded designs. We found that the generated solutions closely match the results obtained from our hand-coded designs, showing merit for our approach. Our plans for future work include refining the tool-flow, further optimizing the generated code, and performance testing of a wider range of SDR applications.