Techniques for minimizing area and power in test pattern generation
Kalyani Jagtap, Shubhangi V. Rathkanthiwar, Sandeep Kakde, Hemant Pendharkar · 2017
In VLSI system testing is an crucial process for making the assurance functionality of the chip. In this paper we are focusing on different techniques for generating test pattern. BIST is a Design for Testability (DFT) technique, because it makes the electrical testing of a chip easier, faster, more efficient, and less costly. To overcome the number of transitions, area overhead and switching activity DS-LFSR based TPG is used. Dual-speed LFSR consists of two registers (LFSRs), a slow LFSR and normal-speed LFSR. The slow LFSR is operating by slow clock whose speed is 1/dth that of normal clock, which operate the normal-speed LFSR. A MSIC-TPG designed and developed a reconfigurable Johnson counter and a scalable SIC counter to generate a class of minimum transition sequences. The merits of multiple single input change patterns are minimum transition, uniform distribution and uniqueness of patterns. The switching activity required for test pattern generation has been improved and area overhead has been reduced is presented in this paper. This paper is implemented using Xilinx 13.1 ISE design suite in Verilog HDL.