Design and implementation of low power test pattern generator using low transitions LFSR
Tejas Thubrikar, Sandeep Kakde, Shweta Gaidhani, Shailesh D. Kamble, Nikit Shah · 2017
The testing of VLSI circuits entitles many challenges in term of area overhead, power and latency. The Low transition test pattern generation is a very crucial technique for testing of a complex architecture of VLSI design. In this paper, 32-bit test pattern generator has been proposed for testing the VLSI design. This 32-bit test pattern generator is implemented with efficient LFSR and with extra combinational circuitry which achieved Low power consumption. This paper is implemented using Xilinx 13.1 ISE design suite in Verilog HDL. The switching activity between the tests vector are reduced, this results in low power consumption. The design of test pattern generation which yield a power of 23 mW with a latency of 5.194ns. The switching activity required for 32-bit test pattern generation has been improved and presented in this paper. The experimental result shows that the total power in low transition linear feedback shift register is 50.06% less than the conventional LFSR.