A high-speed single-path delay feedback pipeline FFT processor using vedic-multiplier
Tapsi Gupta, Janki Ballabh Sharma · 2017 International Conference on Information, Communication, Instrumentation and Control (ICICIC) · 2017
FFT processors are playing vital role in modern orthogonal multi-carrier based communication systems. Due to large number of users and portability requirements, high throughput and high speed are the basic requirements of these systems. In this paper a high-speed single path delay feedback (SDF) pipeline FFT processor using Vedic-multiplier is proposed. Proposed architecture is memory-less and employs Radix-2 butterfly, reconfigurable complex constant Vedic multiplier and delay elements. Reconfigurable complex constant Vedic multiplier designed by using Urdhvatiryakabhyam sutra of Vedic multiplication, offers advantages such as high-speed, small area etc. Simulation results shows that proposed scheme is having high speed, high throughput and smaller area and verifies its efficacy in comparison to conventional architectures. Proposed architecture is suitable to use in OFDM, WiMAX and wireless personal area network (WPAN) systems.