Autotuning high-level synthesis for FPGAs using OpenTuner and LegUp
Pedro Bruel, Alfredo Goldman, Sai Rahul Chalamalasetti, Dejan S. Milojicic · 2017
Changes in Moore's law and Dennard's scaling made hardware accelerators critical for performance improvement, but configuring them for performance, area, and energy efficiency is hard and requires expert knowledge. High-Level Synthesis (HLS) tools enable hardware design for FPGAs to be done in high-level languages reducing the cost and time needed but still requiring configuration. This paper presents an open-source, flexible and virtualized autotuner for LegUp High-Level Synthesis parameters. Our optimization target was the Weighted Normalized Sum (WNS) of 8 hardware metrics. Weights were used to define 3 optimization scenarios targeting Area, Performance & Latency and Performance, plus a Balanced scenario. The autotuner found optimized HLS parameters that decreased WNS by up to 16% in the Balanced scenario, 23% in the Area scenario, 23% in the Performance scenario and 24% in the Performance & Latency scenario. This approach enables autotuning High-Level Synthesis parameters for different objectives by selecting weights for hardware metrics.