VLSI Hardware Architecture of Real Time Pattern Classification using Naïve Bayes Classifier
Priyanka Chaudhary, Manish Kumar Sharma · 2017
In this paper, we present VLSI architecture of Naïve Bayes classifier for multi-classification on FPGA. The objective of this work is to facilitate real time classification of the facial expressions into seven categories: happy, surprise, sad, disgust, fear, anger and neutral, which could be used in any monitoring system including lie detector. Thus, the challenge here is to achieve good performance without compromising the accuracy of the classifier. The need to process the images in real time, lead to implementation of hardware that offers parallelism, are robust and thus considerably decrease the processing interval. Thus, we decided to use Xilinx System Generator for designing hardware architecture. XSG is a very useful tool for developing computer vision algorithms.