An Efficient Architecture for Double Precision Floating Point Adder with LOA
Reddy, S. Rajasekhar, M. Kalapana Chowdary, P. Kanvitha · Zenodo (CERN European Organization for Nuclear Research) · 2017
Because of dynamic representation capabilities and a large spectrum of numbers can be represented with a limited number of bits, floating-point numbers are being widely adopted in the fields of scientific applications. A floating-point arithmetic unit is specifically designed to carry out on floating-point numbers and is one of the most common parts of any computing system in the area of binary applications. Floating-point additions are the most frequent floating-point operations and floating-point adders are therefore critically important components in signal processing and embedded platforms. This review paper presents the survey of related works of different algorithms/techniques which are important for implementation of double precision floating point adder with reduced delay based on FPGAs. In this paper, an area and delay efficient floating-point adder are proposed by approximately designing an exponent subtractor and mantissa adder. Related operations such as normalization and rounding are also dealt with in terms of inexact computing.