Map-scan node accelerator for big-data
Mihaela Maliţa, Ștefan Gheorghe · 2017
The current hybrid architectures, used to accelerate the nodes of the various distributed computing systems running Big Data applications, are mainly based on Nvidia's GPU or Intel's MIC accelerators. These accelerators are marked by limitations due to their too general and ad hoc structural and architectural features. In this paper, we propose a Map-Scan architecture, as a generalization of a Map-Reduce architecture, more appropriate for the parallel approach in defining the accelerator part of a hybrid system. The paper describes the organization and the architecture of a hybrid system based on our Map-Scan Accelerator (MSA). The degree of parallelism achieved by our proposal is compared with the current implementations. The energy consumption is estimated, by simulation, for the ASIC versions of MSA. We conclude that the Map-Scan approach in defining the accelerator of a hybrid system provides the appropriate solution for accelerating various Big Data applications and linear algebra based applications.