Implementation of an efficient dynamic AES algorithm using ARM based SoC
B. K. Balasubramanya Raju, Ashwin Krishna, Geetishree Mishra · 2017 4th IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics (UPCON) · 2017
The AES algorithm is the most extensively used security algorithm in the modern era. From the primitive ECB mode developed by Rijndael, the algorithm has evolved into a plethora of intricate modes, most notably the CTR, CBC and its numerous variants. Although these modes present a modest result, there exists an onerous task of dealing with a convoluted approach. Thus the tradeoff between the complexity of the result and the simplicity of implementation is an aspect worthy of being discussed. With the accretion of the embedded systems domain, efficient hardware implementation of the AES algorithm becomes imperative to buttress the low cost attribute of this domain. This paper describes the implementation of our modified AES algorithm using an ARM Cortex M4 platform. The traditional algorithm and its variants always yield a static cipher when the plain text and key are the same. Using intrinsic processor capabilities the algorithm was modified such that a dynamic nature was injected into the cipher. Thus when the plain text and key remain static, the cipher always varies. Furthermore, the algorithm is able to decrypt the dynamic cipher without compromising on the strength of algorithm. The size of the key used was 128bits long. The block size used was of the same length. Using standard inputs, keys and initialization vectors, the cipher texts were compared with that of typical modes with respect to its variance. Additionally, the algorithm was tested for the avalanche effect to reiterate its tenacity. The outcome of our modified algorithm with respect to traditional methods in terms of variance, bit variability and avalanche coefficient are presented in this paper.