A fast HDL model for full-custom FPGA verification
Kaixuan Zhang, Zhihua Feng, Hao Zhou · 2017
Verification occupies an important role in design of full-custom Field Programmable Gate Array (FPGA). In general, a full-custom FPGA is manually designed in the transistor level. However, it is normally too slow for conventional Electronic Design Automation (EDA) software to run the full-chip transistor-level simulation and verification efficiently. In order to solve this problem, we propose a methodology to build a fast Hardware Description Language (HDL) model for FPGA, which can then be simulated by EDA tools in the multi-core mode efficiently and conveniently. We build an automatic platform based on the methodology to generate the HDL model and a verification platform to realize a fast and convenient functional verification for a full-custom FPGA. As an experiment, an internally developed twenty-million-transistor FDP FPGA [1] is used to verify the efficiency of the platforms. In our experiment, it takes 3.65h to verify the model of the internally developed twenty-million-transistor FPGA with 32-core simulation.