A dynamic test compaction method on low power test generation based on capture safe test vectors
Toshinori Hosokawa, Atsushi Hirai, Hiroshi Yamazaki, Masayuki Arai · 2017
In at-speed scan testing, capture power is a serious problem because the high power dissipation that can occur when the response for a test vector is captured by flip-flops results in circuit-damaging high temperature and timing errors, which may cause significant capture-induced yield loss. A low capture power test generation method based on fault simulation using capture safe test vectors in an initial test set was proposed to resolve a high capture power problem. In this paper, we propose a dynamic test compaction method on the low capture power test generation to reduce the number of capture-safe test vectors. In the dynamic test compaction, faults to satisfy the following conditions are selected as secondary faults. The conditions are that fault excitation cubes of secondary faults are compatible with that of a primary fault and secondary faults are located in fanout-free regions which are sensitized by a test vector for a primary fault. Experimental results show that this method reduces the number of capture-safe test vectors by 18% on average.