An efficient built-in self-repair scheme for multiple RAMs
Arathy S Nair, P L Bonifus · 2017
Vast advancements in the semiconductor domain, approach of integrated chip design, availability of many integrated circuit (IC) packaging strategies and efficient IC test techniques have efficiently contributed towards the incorporation of entire system on one chip (SOC). The increasing trend of SoC technology, highly reliable embedded memories having high density and good yield are required for effective implementation of the system. While manufacturing a chip, yield improvement of the memories is one important aspect that one has to consider. In todays SoCs, a huge percent of the chips area is utilized by memories. So memories as they are designed and optimized as per the limits of the technology, are often prone to failures. It is crucial for the SoC products that the memory cores should be reliable and should provide a reasonable level of yield. This is the reason why a Built-In Self-Repair Technology is earning importance. Built in self repair (BISR) methodology is an efficient self repair technique that can be used in the repair process of the memories (RAMs). Repairing of memories is necessary, because just detecting errors is no longer sufficient for SoCs, therefore both diagnosis and repair techniques are required. If each RAM in an SOC possess its own dedicated BISR (DeBISR) circuit, results in large area consumption. Such a dedicated in built repair technology for each RAMs in SOC also leads to high cost. In that case it is significant to have a Re-Configurable Built in Self Repair (ReBISR) circuitry which can be shared by multiple RAMs and hence the total area and cost of BISR circuits in an SOC can be drastically reduced. In this work a Re-configurable Built in Self Repair (ReBISR) that can repair multiple RAMs by incorporating both 2-D and selectable redundancy is presented. TPG used for generating memory address is the complete linear feedback shift register (CLFSR) which consumes much less area compared to any other address generation unit. March C-algorithm is used as the testing algorithm as it provides sufficient fault coverage with minimum test length. The defective RAMs are allocated to non-defective redundant elements using an effective algorithm called redundancy allocation algorithm. The three basic building blocks are; A Repairable RAM, BIST module and a BIRA module. Xilinx ISE 14.2 is used to implement the BISR architecture.