Implementation of Multi-Priority Variable-Length iSLIP Algorithm Based on FPGA
Hui Xu, Xue Sun, Cao Su-zhi, Zhan Yueying · 2017
At present, crossbar-based exchange structure has become the mainstream of building large-capacity switches. The iSLIP (iterative round-robin matching with slip) algorithm has been widely used because of its easy to achieve, can achieve 100% throughput and other advantages. But the current research on iSLIP algorithm is for fixed-length cells. In order to improve the bandwidth utilization of the iSLIP algorithm, we improve the iSLIP algorithm to support variable-length cell scheduling, and provide multi-priority support in order to achieve priority service forwarding and reduce its waiting time. We use the FPGA(Field-Programmable Gate Array) to achieve an 8x8 port switching structure, the internal bandwidth achieves 128Gbps. Through the performance analysis, it shows that the algorithm has a good throughput rate and delay characteristics building up the foundation for the future construction of large-capacity multi-level switch fabric.