Reconfigurable and Memory-Efficient Cyclostationary Spectrum Sensor for Cognitive-Radio Wireless Networks
Mahesh S. Murty, Rahul Shrestha · IEEE Transactions on Circuits & Systems II Express Briefs · 2018
This brief proposes a new selective-sampling technique that enables spectrum sensing of orthogonal-frequency division multiplexing primary users with 64, 128, 256, 512, and 1024 subcarriers for contemporary cognitive-radio wireless networks. Reconfigurable and memory-efficient very-large scale-integration architecture of the time-domain cyclostationary detector, based on this new technique, has been designed for spectrum sensing. In addition, we present robust coordinate rotation digital-computer architecture for our detector that reduces the computational error to achieve adequate performance. Our detector is post-layout simulated in 90-nm CMOS process and field-programmable gate array implemented that processes the real-world signals captured using universal-software radio peripheral transceivers. In comparison with the state-of-the-art technique, this design alleviated memory requirement by 99% and other hardware resources by 33%.