Full custom design of adaptable montgomery modular multiplier for asymmetric RSA cryptosystem
Trio Adiono, Hans Ega, Hans Kasan, Syifaul Fuada, Suksmandhira Harimurti · 2017
The asymmetric RSA cryptosystem requires modulo operations in its encryption and decryption process, which is often realized with Montgomery modular multiplication. In this paper, we proposed a Montgomery multiplier hardware design using only primitive gates, adders, shifters, multiplexers, and registers. Our algorithm is also adaptable, which means that it can be reconfigured for applications with any arbitrary bits. The algorithm involves iteration, and to achieve less transistor count, we realized the iteration by feeding back the calculation results at the output back to the input, instead of connecting the gates in series. These considerations are made to allow us to create a compact custom ASIC design. The design was made with 130nm standard CMOS technology with NMOS and PMOS base width of 0.5|jm and 1 urn respectively. With the algorithm, our 8-bit multiplier ASIC design occupies an area of 0.0266mm2. The design is created and verified with Mentor Graphics™ EDA tools.