Study of 64-bit booth asynchronous multiplier based on FPGA
Xiaoqing Liu, Anping He, Caihong Li, Guangbo Feng, Jilin Zhang · 2017
A design of energy-efficient Booth asynchronous multiplier based on two-phase handshake protocol with “bounded bundle data” is presented. By following the asynchronous design methodology, the data processing can isolate from the control so that it would reduce the coupling of each function and simplify control circuit. In this paper/thesis, the algorithm consists mainly of three blocks, namely local multiplier, compressor and look-ahead adder. On this basis the whole multiplier also adopts asynchronous loop structure to increase reusability of the module and reduce power consumption. What's more, this circuit is designed and then accurately achieves synthesis and post-implementation timing simulation with the FPGA of the 28nm technology.