A study on partial reconfiguration with compression via modularizing secondary processes of a general purpose processor
Eimabelle Soriano Clavo de Comer, Vance Anthony Mendez Coronel, Yves Lean Krishner Macayana, Lorenzo Martin Fernandez Manalac, Alexis Czezar Cruz Torreno, Louis P. Alarcón, Maria Theresa de Leon, Chris Vincent Densing, Marc Driz Rosales, Rico Jossel Maestro · 2017
As transistors decrease its size due to scaling, digital circuit capabilities increase. These increases are evident in terms of area, power, and speed. Due to the small nature of these devices, introducing parallel paths further increases functionality. Certain characteristics of FPGAs provide alternatives to achieve these improvements in a similar fashion. Partial reconfiguration(PR) further improves these characteristics by allowing an FPGA to reprogram itself using modules that can be loaded without disrupting existing functions. However, there are limited studies that explore partial reconfiguration and techniques that can be used to improve metrics such as area, speed, and power. The study aims to determine the effects of partial reconfiguration and various techniques, such as a custom controller and decompression, on area, speed, and power by using a general purpose processor with modularized secondary processes. The results of the study show that area of the design was reduced to 43% of the original design, reconfiguration time takes as fast as 10 ms, and power overhead due to PR was negligible with the use of partial reconfiguration. The results of the study open the possibility for complicated designs to be programmed onto smaller devices allowing for a wider range of applications.