Circuit and Methodology for Testing Small Delay Faults in the Clock Network
Shao-Fu Yang, Zhiyuan Wen, Shi‐Yu Huang, Kun-Han Hans Tsai, Wu-Tung Cheng · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2018
A clock network is not only difficult to design, but also challenging to test. For high-performance designs with a rigorous clock-skew requirement, small defects in a clock tree network could lead to unexpected failures in the field and thus need to be identified during the manufacturing test. In this paper, we present a novel flush test procedure to determine if a clock network has any small delay faults. This method does not require any change of the clock network, but it does require a “special test clock signal,” which can be generated on the chip by using only standard cells. Experimental results of transistor-level simulation on benchmark circuits injected with resistive open defects in the layout show that the proposed method is capable of detecting a delay fault as small as 52.8 ps.