Three operand fused floating point add-subtract unit using redundant adder
Prachi Palsodkar, Prasanna Palsodkar · 2017
In this paper an efficient fused three operand floating point add-subtract unit is designed using Binary Signed Digit (BSD) adder. BSD adder-subtractor improves overall speed of addition due to its carry limited operation. BSD adder delay reduces by 28% and 17% compared to carry save adder (CSA) and ripple carry adder (RCA) respectively. Three operand adder performs two additions in a single unit which reduces overall critical path compared to discrete and two term computation. It shows 25% reduction in delay and 14% reduction in area compared to three term computation using discrete unit. It will be an enhanced way-out for most of the algorithms with multiple additions.