Buffer aware arbiter design to achieve improved QoS for NoC
Afshan Amin Khan, Roohie Naaz Mir, Najeeb-ud-Din · 2017
In order to meet the need for high-speed data processing, system designers have adopted Multi-Processor System-on-Chip (MPSoC) design. Network-on-chip (NoC) promises to be a viable solution as the basic communication fabric for such designs. A router is the basic component of NoC and using efficient internal blocks to design a router is expected to improve the performance of a router as a whole. One such block of prime importance is an arbitration unit. The commonly used arbitration logics include Fixed Priority, Lottery and Round Robin algorithm. However, they lack the capability of dynamically changing the priority according to data flit rates of specific ports. Thus a requester sending more requests can suffer from starvation and ultimately loss of data if not served within due course of time. In this work, we propose an improved Round Robin algorithm, for increasing Quality-of-Service (QoS) of a router. This is achieved by making use of an additional control signal from the buffer of each input port named as Buffer full (b_f). This addition will help us avoid the starvation condition of input ports which have more data flits to send than the lightly loaded input ports. The superiority of the proposed method than the conventional one is its feasibility for non-uniform traffic applications. All the circuits are implemented using Vivado 2016.2, with Zed-board as the target board. The proposed design is expected to find its application in areas where the traffic pattern is not certain and can vary from uniform to hot-spot traffic.