Security of several AES Implementations against Delay Faults
Olivier Faurax, Julien Francq · 2007
Among fault attacks, Differential Fault Analysis is the most studied attack scheme, but some corresponding fault model are presented as unrealistic (ex: one bit-flip only). Glitches on the power supply, if they induce delays on the whole cir-cuit, may lead to such fault model, depending on the accuracy of the glitch duration and on the design. In this paper, the sensitivity of several AES implementations towards delay faults is analysed. It appears that some fault cryptanalysis can easily be applied to the most sensitive implementations and that designers have to consider even the most unrealistic threats. 1