Reliability in Floating-Gate NAND Flash Memory Devices
조성민 · Seoul National University Open Repository (Seoul National University) · 2015
As flash memory cells continue to decrease in scale, random telegraph noise (RTN) caused by electron capture or emission at trap sites has become an important issue.Fluctuations in the threshold voltage (ΔV th ) due to RTN can cause serious problems, such as read errors and device instability.As the thickness of the inter-poly dielectric IPD continues to decrease, the traps in the IPD also lead to reliability issues related to the leakage current and data retention.In this thesis, we investigate the reliability of NAND flash memory with respect to traps not only in the tunneling oxide but also in the IPD of the cell device.We first focus on traps that produce RTN in the tunneling oxide during a read operation.The trap position with respect to the channel surface and the floating-gate (x T ) and the trap position along the channel length direction (y T ) in the fabricated NAND flash memories were obtained by considering the channel resistance of the pass cells.The RTN in the floating-gate NAND flash cell strings interfered with the adjacent bit-line cell, and the effects of such on the fluctuations in the bit-line current (ΔI BL = high I BL -low I BL ) were characterized.The electron current density (J e ) of a read cell was found to be appreciably different depending on the position in the channel width direction relative to the effect of the interference on the adjacent cells.A characteristic function [g(z)] with a Gaussian functional form is defined based on L t and the trap position within the tunneling oxide from the channel surface (x T ).Finally, ΔI BL is extracted by integrating f(z) and g(z).Our model accurately predicts ΔI BL , with the trap position as a parameter of the state of the bit-line cells, showing good agreement with data from a 3-D simulation.