MLC/3LC NAND flash SSD cache with asymmetric error reduction huffman coding for tiered hierarchical storage
Hikaru Watanabe, Yoshiaki Deguchi, Ken Takeuchi · 2017
Asymmetric Error Reduction Huffman Coding (AERH) is proposed for MLC/3LC NAND flash memory used as SSD cache in the tiered hierarchical storage. AERH compresses data, reduces asymmetric memory cell errors by modulating Vth distribution and thus enhances reliability and endurance of memory cells. AERH decreases data-retention errors by 72.6% and 82.6% of MLC and 3LC NAND flash, respectively. In addition, this paper analyzes the compression ratio and the cost (effective bits/cell) of proposed AERH. Proposed MLC/3LC NAND flash with AERH realizes the utmost reliability of enterprise SSD cache where SLC NAND flash is commonly used.